// Licensed under the Apache License, Version 2.0 or the MIT License.
// SPDX-License-Identifier: Apache-2.0 OR MIT
// Copyright Tock Contributors 2022.

//! Named interrupts for the E310-G003 chip.

#![allow(dead_code)]

pub const GPIO0: u32 = 1;
pub const GPIO1: u32 = 2;
pub const GPIO2: u32 = 3;
pub const GPIO3: u32 = 4;
pub const GPIO4: u32 = 5;
pub const GPIO5: u32 = 6;
pub const GPIO6: u32 = 7;
pub const GPIO7: u32 = 8;
pub const GPIO8: u32 = 9;
pub const GPIO9: u32 = 10;
pub const GPIO10: u32 = 11;
pub const GPIO11: u32 = 12;
pub const GPIO12: u32 = 13;
pub const GPIO13: u32 = 14;
pub const GPIO14: u32 = 15;
pub const GPIO15: u32 = 16;
pub const GPIO16: u32 = 17;
pub const GPIO17: u32 = 18;
pub const GPIO18: u32 = 19;
pub const GPIO19: u32 = 20;
pub const GPIO20: u32 = 21;
pub const GPIO21: u32 = 22;
pub const GPIO22: u32 = 23;
pub const GPIO23: u32 = 24;
pub const GPIO24: u32 = 25;
pub const GPIO25: u32 = 26;
pub const GPIO26: u32 = 27;
pub const GPIO27: u32 = 28;
pub const GPIO28: u32 = 29;
pub const GPIO29: u32 = 30;
pub const GPIO30: u32 = 31;
pub const GPIO31: u32 = 32;
pub const UART0: u32 = 33;
pub const UART1: u32 = 34;
pub const QSPI0: u32 = 35;
pub const SPI1: u32 = 36;
pub const SPI2: u32 = 37;
pub const PWM0CMP0: u32 = 38;
pub const PWM0CMP1: u32 = 39;
pub const PWM0CMP2: u32 = 40;
pub const PWM0CMP3: u32 = 41;
pub const PWM1CMP0: u32 = 42;
pub const PWM1CMP1: u32 = 43;
pub const PWM1CMP2: u32 = 44;
pub const PWM1CMP3: u32 = 45;
pub const PWM2CMP0: u32 = 46;
pub const PWM2CMP1: u32 = 47;
pub const PWM2CMP2: u32 = 48;
pub const PWM2CMP3: u32 = 49;
pub const I2C: u32 = 50;
pub const WATCHDOG: u32 = 51;
pub const RTC: u32 = 52;
